ASIC design verification experience of 3-5 years.
Understanding or technical expertise in functional verification of microprocessor designs.
Experience with Verilog/System Verilog HDL, programming in Perl/Python/Ruby, C/C++, Makefile and logic simulation.
Experience with x86, ARM or any other industry standard microprocessor architecture.
Strong understanding of computer architecture and assembly programming, preferably x86.
A passion for computer architecture and a good understanding of modern out-of-order superscalar processor architecture.
Strong understanding the design and verification life cycle.
Experience in CPU cache/memory subsystem verification is a plus
Simulation and debugging with a Verilog-based functional simulator.
General functional verification experience with digital designs.
Working experience in UNIX software environment.
Strong problem-solving and debugging skills in both pre
and post-silicon environments.
