Greetings!!!!
Job Title: VLSI Design Trainer (RTL to GDSII Flow)
- Location: Madurai / Hosur
- Duration: 14 Weeks
- Mode: Classroom
- Experience: 3+ Years in VLSI Design & Training (Preferred)
Job Summary
We are looking for an experienced VLSI Design Trainer to deliver hands-on training covering the complete VLSI Design Flow from RTL to GDSII. The ideal candidate should possess strong industry experience in digital design, RTL coding, verification, synthesis, static timing analysis (STA), physical design, and sign-off. The trainer should be capable of delivering both theoretical concepts and practical lab sessions using industry-standard EDA tools.
Key Responsibilities
- Deliver instructor-led classroom training on the complete VLSI Design Flow from RTL to GDSII.
- Teach Digital Design fundamentals, RTL design, and Verilog/SystemVerilog programming.
- Explain Front-End and Back-End VLSI methodologies and industry best practices.
- Conduct hands-on laboratory sessions on RTL coding, simulation, and waveform debugging.
- Train students in RTL verification using Verilog/SystemVerilog and testbench development.
- Explain synthesizable and non-synthesizable coding constructs and RTL coding guidelines.
- Deliver sessions on Logic Synthesis, Static Timing Analysis (STA), and timing closure concepts.
- Guide students in applying timing constraints and analyzing synthesis reports.
- Conduct practical sessions on Physical Design, including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and Sign-Off.
- Train participants on Design Rule Check (DRC), Layout Versus Schematic (LVS), and GDSII generation.
- Introduce Design-for-Testability (DFT), Scan Chains, ATPG, BIST, and low-power design techniques.
- Mentor students through an end-to-end mini project covering RTL development, synthesis, STA, Physical Design, and GDSII generation.
- Provide live demonstrations, hands-on exercises, assignments, and project guidance.
- Evaluate student performance and provide continuous technical support throughout the training.
Required Technical Skills
- Strong understanding of Digital Electronics and Finite State Machine (FSM) Design.
- Hands-on experience with Verilog and SystemVerilog.
- Good knowledge of RTL Design, Simulation, and Functional Verification.
- Experience with Logic Synthesis and Static Timing Analysis (STA).
- Understanding of Physical Design flow, including Floorplanning, Placement, CTS, Routing, DRC, LVS, and Sign-Off.
- Knowledge of Design-for-Testability (DFT) concepts.
- Familiarity with Low-Power Design methodologies.
- Ability to explain semiconductor design concepts in a practical and easy-to-understand manner.
Tools Exposure
Candidates should have experience with one or more of the following tools:
- Verilog / SystemVerilog
- ModelSim / QuestaSim
- Icarus Verilog
- GTKWave
- Verilator
- Yosys
- Synopsys Design Compiler
- OpenSTA
- PrimeTime
- OpenLane
- Cadence Innovus
- Synopsys ICC2
- Magic
- KLayout
- Calibre
Preferred Qualifications
- Bachelor's or Master's degree in Electronics, Electronics & Communication (ECE), Electrical Engineering, VLSI, or a related discipline.
- 3–8 years of industry experience in VLSI Design and/or Technical Training.
- Prior experience in delivering classroom or corporate technical training is highly preferred.
- Excellent communication, presentation, and mentoring skills.
Training Delivery Mode
- Theory Sessions
- Live Demonstrations
- Hands-on Practical Labs
- Assignments & Assessments
- End-to-End Mini Project
- Interview Preparation & Technical Guidance
Pay: ₹5,000.00 - ₹7,000.00 per day
Work Location: In person
