B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 1 year of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at block level for multiple tape outs. With Block level hands on experiences in most of the following:.
- Block level floor planning, power planning and IR drop analysis.
- Timing closure with Xtalk and OCV
- Multimode multi corner optimization and closure.
- Clock tree synthesis and advanced clock tree implementation.
- Blocks sizes upward of 400K Instances to 2M Instances.
- Block level timing closure with sign off STA.
- Block level ECO implementation involving netlist level logical changes.
- Scripting experience in Perl/TCL.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions.
- Low power technologies exposure.
- Technologies from 28nm and below.
- Physical Verification experience in advance nodes.
send your resumes to [email protected]
