EXPERIENCE LEVEL: Mid (3-5 years)
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ABOUT STRATUM DEFENSE TECHNOLOGY
Stratum Defense Technology LLP is an Indian defence technology company building autonomous systems for the Indian armed forces. We are at the founding stage, developing India's first indigenous autonomous undersea vehicle under the iDEX ADITI 4 programme. NSTL Visakhapatnam (DRDO) has issued a formal Letter of Support for our application.
We are headquartered in New Delhi with programme operations at Visakhapatnam. The people joining now will be present at every significant programme milestone.
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ABOUT THE ROLE
You will own the electronics hardware development lifecycle for an autonomous undersea vehicle — from first schematic to validated PCBA in the field. This is a hands-on engineering role, not a review or coordination role. You will design circuits, create PCB layouts, drive fabrication and assembly, and lead board-level bring-up and debug on hardware that operates in a demanding, safety-critical environment.
You will work cross-functionally as the hardware layer connecting firmware, autonomy, power, and mechanical subsystems — defining interfaces, managing the product development plan, and ensuring hardware deliverables hit programme milestones.
Full technical scope shared under NDA at first interview stage.
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RESPONSIBILITIES
- Own schematic design for power management, motor drive interfaces, sensor front-ends, communication subsystems, and vehicle control electronics
- Create multi-layer PCB layouts: mixed-signal, controlled impedance, power plane design, and high-density connector interfaces to IPC-2221 and IPC-2141 standards
- Drive the full PCBA development cycle: BOM generation, component selection, DFM review with PCB manufacturers, Gerber / ODB++ release, and assembly coordination
- Lead board bring-up, functional validation, and debug; write and execute test procedures with traceable acceptance criteria
- Define and maintain the Product Development Plan (PDP) for all electronics hardware deliverables across programme milestones (PDR, CDR, FAT)
- Own cross-functional hardware integration — interface definition, signal and power budgets with firmware, propulsion, acoustic sensor, and autonomy subsystems
- Perform PDN simulation and signal integrity analysis: impedance, transient response, differential pair management, EMI coupling between power and signal domains
- Support MIL-STD-461G EMC design practice from architecture through qualification testing
- Manage component selection, approved parts list, and obsolescence across the programme
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ESSENTIAL REQUIREMENTS
- BTech or MTech in Electrical or Electronics Engineering
- Schematic capture and PCB layout at production drawing standard: Altium Designer, KiCad, or OrCAD
- End-to-end PCBA development: DFM review, Gerber release, assembly coordination, and board bring-up
- Mixed-signal PCB design: power and signal domain separation, decoupling strategy, controlled impedance routing
- PDN analysis and signal integrity: plane splits, ripple margin, EMI coupling management
- Cross-functional hardware integration experience: firmware interface handoff, subsystem electrical interface definition
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BENEFICIAL EXPERIENCE
- Defence, aerospace, or marine electronics hardware development
- MIL-STD-461G EMC design and test
- High-reliability PCBA: conformal coating, potting, MIL-DTL-38999 connector interface design
- Battery management system hardware and DC-DC power stage design
- SPICE, HyperLynx, or Sigrity PDN simulation
- IPC-610 inspection standard familiarity
- BEL, ISRO, HAL, DRDO, or defence electronics background
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WHAT WE OFFER
- Work on a programme that does not exist anywhere else in India
- Direct access to NSTL Visakhapatnam test facilities and DRDO research community
- Salary Rs 4.56–9 LPA benchmarked to Delhi defence-adjacent market
- Hybrid working with flexibility outside critical programme milestones
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HOW TO APPLY
[email protected]
Subject: JD07 Hardware Design
CV and a short note on a PCB you have designed end-to-end — what it does, which EDA tool you used, and whether you took it through fabrication and bring-up yourself. No cover letter.
Pay: ₹456,133.05 - ₹900,000.00 per year
Ability to commute/relocate:
- Delhi, Delhi: Reliably commute or planning to relocate before starting work (Preferred)
Application Question(s):
- Have you performed signal integrity analysis — controlled impedance routing, differential pair management, or EMI coupling review?
A) Yes — using a dedicated SI tool (HyperLynx, ADS, Sigrity, or equivalent)
B) Yes — using SPICE simulation or manual calculation
C) Yes — applied impedance rules in layout without simulation
D) No
- Which EDA tools have you used for schematic capture and PCB layout? Select all that apply.
A) Altium Designer
B) KiCad
C) OrCAD / Cadence
D) Eagle
E) Zuken / CADSTAR
F) Other (specify in application note)
G) None
- Do you have experience designing electronics for any of the following environments? Select all that apply.
A) Defence or aerospace (MIL-STD, DO-160, or equivalent)
B) Marine or underwater systems
C) Automotive or industrial (harsh environment, vibration, thermal)
D) DRDO, BEL, ISRO, HAL, or defence PSU background
E) Consumer / commercial only
- Have you taken a PCB design from schematic through to Gerber / ODB++ files and coordinated fabrication with a PCB manufacturer?
A) Yes — I owned the full cycle including DFM review and fab coordination
B) Yes — I produced the files but fabrication was handled by someone else
C) No
- What is the highest layer count PCB you have designed, and was it mixed-signal (power and signal domains on the same board)?
A) 6+ layers, mixed-signal
B) 4 layers, mixed-signal
C) 4 layers, single domain (power only or digital only)
D) 2 layers only
- Have you designed a power distribution network on PCB — copper pours, plane splits, decoupling placement, and PDN impedance?
A) Yes — including PDN simulation (HyperLynx, Sigrity, SPICE, or equivalent)
B) Yes — by hand calculation and layout practice, no dedicated tool
C) Partial — followed existing design rules but did not define them
D) No
Work Location: Hybrid remote in Delhi, Delhi
