We are hiring for Senior Staff Engineer for Physical Design team with minimum 8+ years of strong hands on experience in constraints development, timing analysis/closure of large SoCs. Must have good understanding of 22nm/28nm/40nm technologies and associated timing/SI closure challenges. Good with stake holder management.
Your Role
Key responsibilities in your new role
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Responsible for STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.
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Ownership of constraints development for functional/test modes at pre/post layout stage.
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Timing analysis and convergence of large hierarchical design across multiple modes and corners.
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Work closely with physical design team for timing/SI closure.
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Responsible for owning and/or mentoring Synthesis, Equivalence Checks.
Your Profile
Qualifications and skills to help you succeed
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Must have 8 + years of Strong exposure in constraints development, timing analysis/closure of large SoCs
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Expert user of industry standard tools for timing signoff
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Experience in scripting languages (shell, perl, tcl) and Make flow
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Understanding of 22nm/28nm/40nm technologies and associated timing/SI closure challenges
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Understanding of Low Power design techniques
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Experience in low-power synthesis and equivalence checks will be a plus
Contact:
[email protected]
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