Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
- Understanding of the design flow and methodologies used in the designing
- Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills
Additional Comments:
JD- DV (Design Verification) • ASIC IP-level verification using UVM, Verilog, SystemVerilog, C/C++. • Debug firmware/RTL with simulation tools; Linux/Windows environments. • Develop UVM-based frameworks, automate workflows, improve simulation efficiency. • Knowledge of graphics pipeline, SystemC/TLM, scripting (Perl, Ruby, Shell). • Experience with FPGA/emulation, hardware validation, debugging waveforms/logs. • Familiarity with x86/ARM SoC architecture and protocols (PCIe, DDR, USB, etc.). • Leadership/mentorship exposure preferred.
