We are looking for experienced RTL Design Engineers with strong expertise in PCIe Gen6/Gen7 protocol development for high-performance ASIC/SoC designs. The ideal candidate should have hands-on experience in RTL design, micro-architecture development, and integration of high-speed interface IPs in advanced technology nodes.
Key Responsibilities
- Develop RTL design and micro-architecture for PCIe Gen6/Gen7 based subsystems and controllers.
- Work on high-speed protocol design involving PCIe, PIPE, LTSSM, DMA, and controller architectures.
- Perform RTL coding using Verilog/SystemVerilog with focus on performance, power, and area optimization.
- Collaborate with architecture, verification, physical design, and firmware teams for successful SoC integration.
- Analyze and resolve design issues related to timing, functionality, protocol compliance, and performance bottlenecks.
- Participate in design reviews, code reviews, and technical discussions.
- Support synthesis, lint, CDC, low-power checks, and silicon bring-up activities.
- Debug complex RTL and integration issues during simulation and post-silicon validation phases.
Required Skills
- Strong hands-on experience in RTL Design and Micro-architecture development.
- Expertise in PCIe Gen6 and/or Gen7 protocol architecture and implementation.
- Strong understanding of:
- PCIe LTSSM
- Transaction/Data Link/Physical layers
- PIPE interface
- Flow control and error handling
- Equalization and high-speed serial interfaces
- Proficiency in Verilog/SystemVerilog.
- Experience with ASIC/SoC design methodologies and integration flows.
- Good understanding of synthesis, timing closure, CDC, and lint methodologies.
- Familiarity with EDA tools from Synopsys/Cadence/Siemens.
- Strong debugging and problem-solving skills.
Preferred Qualifications
- Experience with CXL, NVMe, or other high-speed protocols is an added advantage.
- Exposure to advanced nodes such as 5nm/3nm is preferred.
- Knowledge of low-power design techniques and UPF is a plus.
- Prior experience in client, datacenter, AI/ML, or networking SoCs preferred.
Educational Qualification
- Bachelor’s or Master’s degree in Electronics/ECE/VLSI/Microelectronics or related field.
Why Join Us
- Opportunity to work on next-generation PCIe Gen6/Gen7 technologies.
- Exposure to cutting-edge semiconductor and high-performance computing projects.
- Collaborative engineering culture with strong technical growth opportunities.
Pay: ₹2,455,765.89 - ₹4,090,091.00 per year
Work Location: In person
