Job Description: Ramaiah Skills Academy is seeking a technical leader to serve as the Lead Application Engineering of VLSI Design. In this role, the incumbent will spearhead the vision, curriculum design and delivery of advanced training programs in RTL Design, Functional Verification, and Digital System Architectures. The incumbent will lead a team of Application Engineers and trainers, establishing industry-standard methodologies to bridge the gap between academia and corporate semiconductor engineering.
The ideal candidate possesses comprehensive, hands-on mastery of frontend VLSI flows, advanced verification methodologies (UVM, SVA), and chip synthesis/timing analysis, alongside the leadership acumen to mentor next-generation VLSI professionals and corporate learners.
The Ecosystem
The Ramaiah Academy Foundation represents a strategic triad uniting education, industry readiness, and commercialization:
- Ramaiah Institute of Science & Management (RISM): A greenfield, next-generation deemed university advancing STEM and Management education through a knowledge partnership with SUNY Albany.
- Ramaiah Skills Academy & Technocentre Engineering (TCE): An elite upskilling engine and industrial R&D consulting arm, bridging the gap between academia and industry.
- VYUHA Deep Science Translational Center: The 360-degree commercialization engine delivering disruptive technology solutions across Aerospace, Semiconductors, Medtech, AI, and Cybersecurity.
Roles & Responsibilities:
- Strategic Leadership & Curriculum Architecture: Define the technical roadmap for the VLSI division. Design, audit, and continuously upgrade high-quality, industry-aligned curricula, assignments, and advanced project frameworks covering Digital Design through to STA.
- Program Delivery & Master Instruction: Deliver high-impact, advanced classroom and online training sessions on complex topics including SystemVerilog OOP, UVM testbench architectures, constrained random verification, and advanced Static Timing Analysis (STA).
- Team & Lab Management: Supervise and mentor a team of Application Engineers and trainers. Oversee the setup, deployment, and maintenance of industry-grade EDA tool flows within the Academy’s laboratories.
- Project Mentorship & Evaluation: Architecture and guide real-time, tape-out quality capstone projects (e.g., RISC-V processors, high-speed interconnects, or hardware accelerators). Establish rigorous evaluation standards and interview preparation strategies.
- Industry Collaboration: Foster deep relationships with semiconductor companies, design houses, and EDA vendors to align training paradigms with contemporary industry constraints and placement demands.
Skill Requirements:
- Core Technical Expertise: Authoritative knowledge of Verilog, SystemVerilog, advanced RTL design principles (FSM design, clock domain crossing, low-power design), and advanced computer architecture.
- Verification Mastery: Deep-dive expertise in the Universal Verification Methodology (UVM), SystemVerilog Assertions (SVA), Functional Coverage modelling, and building complex, reusable constrained-random verification environments.
- Implementation & Sign-off: Thorough understanding of RTL Synthesis, Synopsys Design Constraints (SDC) generation, and Static Timing Analysis (STA) closure methodologies.
- EDA Tool Suite Proficiency: Expert-level command over industry-standard EDA tools from Cadence or Synopsys (e.g., VCS, Verdi, Design Compiler, PrimeTime, Spyglass, Formality, Xcelium, or Genus).
- Soft Skills & Pedagogy: Exceptional communication, lecturing, and leadership skills with a passion for knowledge transfer, talent development, and technical writing.
Pay: ₹255,526.94 - ₹986,673.25 per year
Work Location: In person
