Be part of the Cadence Memory IP Group adn responsible for -
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Developing firmware for DDR/LPDDR/GDDR/HBM PHY using microcontrollers
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Responsible for developing firmware in C and similar Embedded programming languages typically involving bare-metal programming and developing low level APIs on Microcontrollers.
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Responsible for collaborating with hardware designers and memory subsystem architects to derive algorithms and implement them.
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Responsible for collaborating with verification team to deduce firmware-hardware co-verification plan.
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Support debug of firmware-based simulations in hardware behavioral simulations (RTL simulations with firmware for verification)
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Support debugging issues on emulation and Silicon bring-up boards.
Required Skills:
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4-6 years of experience in developing bare-metal firmware for High-speed Serdes or Memory interface Physical Layer blocks.
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Good Knowledge C programming language for embedded software development and use of relevant IDE.
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Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.
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Good knowledge of Shell/Perl/Python/TCL scripting
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Good debugging skills
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Good experience on Verification EDA Tools like simulators and waveform viewers
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Good communication Skill
