Role: Design For Test (DFT) Lead / Manager
Experience: 7 to 14 Yrs
Location: Bangalore / Hyderabad / Kochi
Domain: VLSI/Semiconductor
Required Skills & Experience
- 6+ years of industry experience in DFT for ASIC/SoC designs.
- Strong expertise in:
o Scan insertion & ATPG
o MBIST/LBIST design and integration
o JTAG/Boundary Scan (IEEE 1149.1/1500)
o DFT verification and linting
- Experience with industry-standard EDA tools such as:
o Synopsys (DFT Compiler, TetraMAX)
o Mentor Graphics Tessent
o Cadence Modus
Pay: ₹2,000,000.00 - ₹4,000,000.00 per year
Benefits:
Work Location: In person
