Role description
JD:-
SoC Architecture.
- Validation planning, Post Silicon Validation (C/C++, VC++), working with SystemC based Virtual prototypes (debugging tests at model code level).
- Understands Virtual prototypes (SystemC) capabilities for test development and bring up.
- System level debugging (JTAG, Gdb).
- SW Bring up.
- SW Configuration Management (Rational CC, Git).
HW set ups, HW test equipment (Lauterbach/JTAG, Logic analyzer, Oscilloscope).
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Skills
vlsi design,validation planning,post silicon validation,c,virtual prototypes,sw configuration management,jtag,gdb
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
