At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for physical implementation flows and cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria.
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Working on new processes for physical implementation flows and cutting-edge technology nodes.
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Collaborating with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs.
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Defining signoff criteria with a strong focus on Timing Closure.
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Maturing the physical implementation guide used for customers and internal hardening teams.
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Participating in next-generation physical design methodology and flow development.
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Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff.
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Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints.
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Driving the development of next-generation physical design methodologies and flows.
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Ensuring the optimization and successful implementation of cutting-edge technology nodes.
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Contributing to the development of high-performance silicon chips and software content.
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Enhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria.
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Improving customer satisfaction by maturing physical implementation guides.
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Supporting the achievement of Synopsys' operational goals through innovative design solutions.
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Extensive experience with ASIC design flow and hierarchical physical design strategies.
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Strong background in timing analysis, constraints management, and frontend synthesis.
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Experience with physical-aware synthesis, formality, and various verification strategies.
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Knowledge of Primepower-based power analysis and clock gating for power reduction.
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Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools.
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Strong physical implementation flow debugging skills and scripting abilities.
Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design.
You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
