Bangalore, Karnataka
Job Summary
B.Tech / M.Tech with 2 to 4 years of experience exclusively in DFT.
Strong Digital and STA, VLSI flow, Verilog, Scripting concepts.
Block or Sub-system level:
Hands-on experience to do scan insertion, ATPG DRC, Coverage Analysis, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
Block or Sub-system level:
Hands-on Experience to do MBIST Verification, DFX feature verification, Pattern generation.
Working knowledge of JTAG, iJTAG, ICL, PDL etc.
Good at Communication, self driven VLSI professional
Key Responsibilities
1. Develop And Optimize Scan Chain Structures And Boundary Scan Logic.
2. Implement Mbist/Lbist Features And Validate Their Functionality.
3. Collaborate With Verification Teams For Test Coverage Improvement.
4. Debug Timing And Functional Issues In The Dft Logic.
5. Generate And Review Atpg Patterns For Fault Coverage.
Skill Requirements
1. -Experience With Dft Tools Like Tetramax, Testkompress, Or Modus.
2. -Strong Understanding Of Ieee 1149.1 (Jtag) Standards.
3. -Proficiency In Timing Analysis And Synthesis Tools.
4. -Problem-Solving Skills For Debugging Test-Related Issues.
Other Requirements
1. Optional But Valuable Certifications In Design For Test (Dft) Or Related Areas.
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