Date posted 08/16/2026
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years in the analog and mixed-signal trenches, designing memory circuits that have to work across voltage corners, temperature extremes, and process variations without a second chance. You know that an SRAM bitcell is not just six transistors on a page, it is a tradeoff between read stability, write margin, leakage, and area, and you have made those calls enough times to know which knob to turn when a design is not closing.
You think in terms of transistor-level behavior, not just simulation results. When a memory fails at a corner, you do not just re-run SPICE, you go back to the schematic, check your layout parasitics, and figure out what actually broke. You have worked closely with layout teams, and you understand that a good floorplan s you three weeks of iteration later.
You are comfortable owning a memory block from architecture through tapeout. You can sit with a compiler team and explain why your bitcell needs a specific routing constraint, then turn around and review a layout with a physical design engineer without losing context. At Synopsys, you will design embedded memories that ship in our IP portfolio and power chips across the industry.
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Design and develop embedded CMOS memories including single-port SRAM, dual-port SRAM, register files, and ROM for Synopsys IP products
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Own circuit architecture and transistor-level implementation for ultra-high-speed, ultra-low-power, or high-density memory configurations
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Perform schematic entry, SPICE simulation, layout planning, and supervise physical layout execution through to final verification
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Develop and verify bitcells, define layout rules, and drive layout design and parasitic extraction closure with the physical design team
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Interface with CAD teams to integrate memory designs into compiler automation flows and generate EDA models for customer use
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Collaborate with frontend engineers to define and validate full verification flows including timing, power, and functional models
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Mentor junior engineers and lead technical aspects of memory design projects from concept to delivery
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Your memory designs will ship as part of Synopsys IP offerings used by semiconductor companies worldwide in high-volume production chips
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The bitcells and architectures you develop will define performance, power, and area benchmarks for next-generation embedded memory IP
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Your layout planning and verification rigor will reduce tapeout risk and speed time to market for memory compiler releases
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The automation flows you help define will enable faster, more reliable memory generation for customers across process nodes
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Your technical mentorship will build design capability within the team and raise the quality bar for future memory products
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The tradeoffs you make between speed, power, and density will directly influence customer adoption and competitiveness in the IP market
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Your collaboration with CAD and frontend teams will improve tooling, models, and verification coverage across the memory IP portfolio
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Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related technical field
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Deep hands-on experience with CMOS memory circuit design including SRAM, register files, or ROM
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Proficiency with circuit simulation tools such as HSPICE, Spectre, or similar SPICE-based simulators
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Strong understanding of memory layout design, parasitic extraction, and layout verification tools like Calibre or Assura
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Scripting capability in C-Shell, Perl, or similar languages; experience with C++ or JavaScript is a plus
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Demonstrated ability to lead technical projects and mentor junior engineers through complex design challenges
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Experience working with memory compiler flows, EDA model generation, or design automation is a strong plus
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You can look at a bitcell schematic and immediately spot a read stability issue or a leakage path without running a full simulation
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You know how to work with layout designers, not just hand off a schematic and hope for the best, you review floorplans, flag routing issues, and iterate together
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You are comfortable making technical tradeoffs in ambiguity, choosing between a faster access time and lower leakage when the spec does not give you both
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You can explain a circuit-level design decision to a compiler engineer or a product manager in terms they understand without oversimplifying the engineering
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You stay organized across multiple design blocks, verification runs, and layout reviews without losing track of what is blocking tapeout
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You take ownership, if a memory fails characterization, you do not wait for someone else to debug it, you dig in and figure out what went wrong
Your recruiter will
