Location : Bangalore
Experience : 5 Years
Education : B.E, M.E, M.Tech, B.Tech
Role :
RTL engineers having experience on STA/Synthesis
- Hands on ownership of Synthesis / Constraints / STA / ECO flow.
- Expert in running Block level and Chip level STA in MCMM, DMSA environments.
- Must have worked on multiple timing closure and constraint development for high-speed interfaces like DDR , RGMII, SD, USB, SPI, NAND etc.
- Must have worked on ECO implementation cycles – functional, timing Interacting with RTL/PD/DFT teams to resolve all implementation issues.
- Participate in design reviews and design closure discussions.
- Develop or enhance scripts for various design closure activities.
- Good understanding of complete physical design flow.
- Must have gone through multiple tapeout cycles, revisions and ECOs.
- Expertise with Synthesis, STA tools (like DC, Primetime) is a must.
- Strong scripting skills using Perl, TCL, C-shell, Make and/or other scripting languages.
- Timing characterization and post silicon timing correlation experience a plus.
- Experience/ project work on critical path simulation, clock path simulation (jitter/duty cycle) with Spice a plus.
- Experience with CDC, Constraint verification, lint checks is a plus.
Job Description :
- 5+ Year Experenece RTL engineers having experience on STA/Synthesis
Salary : Open
