Additional Comments:
Job Title: Standard Cell Layout Engineer Location: [ Bangalore ] Experience: [2-8 Years] Job Description: Key Responsibilities: • Perform physical layout design of standard cells and library development to meet performance, area, and power targets. • Work closely with circuit designers to translate schematics into optimized layouts. • Perform floor planning, placement, routing, and device-level layout for standard cells ensuring adherence to design rules (DRC) and layout vs schematic (LVS) checks. • Optimize layouts for high density, performance, and manufacturability. • Conduct parasitic extraction and analysis to meet circuit performance requirements. • Support layout verification, QA, and signoff processes. Required Skills: • Strong knowledge of CMOS technology, layout techniques, and design rules. • Experience in standard cell layout development (basic logic gates, sequential cells, complex cells). • Proficiency in Cadence Virtuoso, Calibre, or similar layout and verification tools. • Good understanding of DRC, LVS, ERC, and parasitic extraction flows. • Ability to work collaboratively in a cross-functional environment with circuit designers and methodology teams. • Attention to detail, strong problem-solving skills, and ability to meet tight schedules. Preferred Qualifications: • Experience in advanced technology nodes (7nm / 5nm / 3nm). • Familiarity with layout automation techniques and scripting (SKILL, Perl, Python). • Exposure to EDA flow enhancements and layout methodologies. Education: • B.E./B.Tech/M.Tech in Electronics, Electrical, or VLSI Design.
