Job Title: Senior Layout Engineer (Analog/RF) : Semiconductor / VLSI domain
Mode: WFO
Location: Bengaluru
Interview: F2F
Key Responsibilities:
Perform IC mask layout design and physical verification for custom Analog/RF mixed signal, IO & ESD designs at the Block/Module level.
Execute and oversee layout activities, including LVS/DRC/antenna checks, for complex mixed-signal integrated circuits.
Collaborate closely with circuit designers and CAD engineers to create and optimize custom Analog mixed-signal blocks layout.
Ensure adherence to established companywide layout design & CAD methodologies and process flows.
Lead and manage a team of 4-5 professionals, providing guidance and support as necessary, and contribute individually when required.
Identify and resolve issues related to failure-prone circuit and layout structures, working in tandem with circuit designers to find optimal solutions.
The candidate should have worked on higher nodes 28nm/40nm & above
We DO NOT need candidates who have worked on lower nodes like 3nm/4nm/8nm etc
Essential Requirements:
Bachelor's degree in a technology-related field with a minimum of 8yrs - 15+ years of relevant experience in layout engineering for Analog/RF domains. Candidates from premier institutes are preferred for all experience levels.
Proficiency in transistor-level floor planning within a multi-voltage, mixed-signal, high-speed, and noise-sensitive environment.
Extensive experience with tools such as Cadence Virtuoso-XL, Virtuoso-L, Mentor Graphics Calibre, Cadence Assura/PVS, and Linux Operating System.
Strong expertise in interpreting and addressing calibre/Assura DRC, LVS, ERC, antenna, and post-layout extraction issues.
In-depth knowledge of Analog layout techniques, CMOS fabrication concepts, and processes.
Excellent communication skills, both verbal and written, with proficiency in creating documents using Microsoft Office and Microsoft PowerPoint.
Familiarity with Latch-up prevention, ESD protection schemes, and an understanding of issues related to RC delay, electromigration, and cross-capacitance.
Proficiency in skill, Perl, C-shell, and TCL programming for automating repeatable layout tasks, and the ability to drive methodology improvements for increased productivity.
Demonstrated ability to customize and optimize rule decks for calibre/Assura DRC/LVS/antenna, driving methodology improvements in layout for productivity enhancements.
Pay: ₹3,000,000.00 - ₹4,500,000.00 per year
Work Location: In person
