Job Title: Principal Engineer, Physical Design
Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office)
Job ID: AI2481
Job Description:
Role & responsibilities:
- SoC/Full-chip integration & P&R Flow Development
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Establishes the integration plans for die with optimization for package and board constraints.
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Bump planning, Die file generation, closing loop with package team on signal and power bump placement restrictions.
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Create physical database for the IP or SoC. Collaborate with architects to optimize the placement of IPs for latency as well as die area/aspect-ratio.
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Collaborate with the design teams on clocking and dataflow to deliver the physical block level floorplans for APR.
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Derive specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies.
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Coordinate with power delivery team on trade-offs for metal allocation for signal and power.
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Have excellent understanding on, die-per-reticle/good-die-per-wafer maximization, and right technology selection on metal layers usage maximization.
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Performs integration of all dies in a package and completes the relevant checks before tape-out.
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Supervise/lead/mentor junior team members.
Minimum Requirements:
- BE/BTech or ME/MTECH with at least 15+ years of experience on high complexity SoC designs. At least one SoC in 7nm or lower.
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Demonstrating knowledge and implementation strategies to create an IO ring in accordance with design specifications.
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Possessing deep knowledge of ESD, latch-up, and other foundry requirements, as well as placement strategies.
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Having hierarchical design implementation knowledge, including partitions/HMs/tiles push down to each core/tile.
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Understanding feed-through planning and implementation.
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PG creation and push-down methodologies.
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Understanding Analog components and their placement requirements according to design specifications.
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Demonstrating RDL knowledge and working with packaging for SoC floorplan design.
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Conducting PV clean-up on floorplan and ensuring self-derivation in all sign-offs, including Physical Verification, ESD, foundry/Analog requirements.
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Working knowledge of PnR implementation, physical verification, and STA
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SoC RTL to GDSII implementation, with top level clocking strategizing and implementation.
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P&R flow owner which includes but not limited to scripting, flow deployment for SoC & Blocks
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Following expertise is a plus:
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In-depth knowledge of Physical Verification tools like in ICC2, Synopsys ICV, ICWBEV.
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Knowledge of Package PV checks, IO/Bump PV cleanup, PV rules viz. Antenna, Density, DFM, DFY, DPT at lower technology nodes 7nm or less.
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Led PV activities on SoC designs with expertise in DRC, LVS, DFM, HV checks and cleanup.
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Expertise in running PV checks on Flat/Hierarchical SoC designs with multiple power domains.
Personal Attributes:
Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.
