Design Verification Engineers / Lead for PCIe Design IP R&D Team at Bangalore
Experience: 4 - 15 Years
Location: Bangalore / Noida
Notice Period: Immediate to 60 Days or serving notice period
Job Description:
We are looking for experienced Design Verification (DV) Engineers and Leads with strong SV / UVM/ Testbench development skills with working knowledge of PCIe /CXL protocol.
Key Responsibilities:
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Lead end-to-end IP verification activities
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Develop detailed test plans and verification strategies
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Build and maintain UVM-based testbenches using System Verilog
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Knowledge of protocols (AXI/AHB/APB ) PCIe is a must.
