Role description
Responsibilities will include but not limited to following:Custom layouts for High-Speed Custom Analog/Digital blocks, such as Ring Oscillators, Dividers, Bias Blocks (Voltage & Current references), pre-drivers etc. in TSMC 2nm & 3nm,Independent in debugging and resolving the layout fixes in various verification flowsFlexible to take different tasks in project.Execute tasks with minimum supervision/tracking,Have accountability and ownership on blocks & tasks assigned.Completed layout designs, with desired quality, with all specified verification flows cleanCreate and check all relevant design views using sign-off tools.Documentation as per requirement. Desired Qualification: B.Tech/B.E./MS /M.E. /M tech in Electrical Engineering5-8yrs of hands-on experience in block/module layouts with Cadence Layout design tools, exp in TSMC 5nm or lower node is mustWell versed with layout design and verification tools - Cadence Virtuoso EXL/GXL, Calibre etc. Knowledge of scripting (SHELL, PERL, SKILL), excel is good to have. Note: 2nm/3nm TSMC NDA required
Skills
vlsi design,cadence,layout,tsmc,analog,debugging,verification,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
