Job Summary
We are seeking an experienced Senior Verification Engineer with 10 years of expertise in top-level SoC verification, specializing in PCIe and DDR subsystems. The ideal candidate will play a critical role in defining verification strategy, leading complex verification efforts, and mentoring junior engineers to deliver high-quality silicon.
Key Responsibilities
- Execute top-level SoC verification for complex designs integrating PCIe and DDR subsystems
- Define and execute verification strategies, plans, and methodologies for full-chip validation
- Develop and maintain UVM/SystemVerilog-based verification environments
- Drive end-to-end verification including integration, performance, and corner-case scenarios
- Ensure robust coverage through functional, code, and assertion-based verification
- Debug and root-cause complex issues across hardware and verification environments
- Collaborate closely with design, architecture, firmware, and validation teams
- Lead PCIe (Gen 5) and DDR4/DDR5 protocol verification and compliance
- Involve in reviews with management on test plans, testcases, and coverage to ensure completeness and quality
- Mentor and guide junior engineers, fostering best practices and technical growth
- Contribute to continuous improvement of verification methodologies and flows
Qualifications
- Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or related field
- 10+ years of experience in SoC verification
- Strong expertise in full-chip verification
- Hands-on experience with PCIe and DDR verification (protocol knowledge)
- Proficiency in SystemVerilog and UVM
- Experience with simulation, debugging, and coverage analysis tools
vlsi design,soc verification,pcie,systemverilog,full-chip validation,uvm,assertion-based verification,ddr,simulation,protocol verification
