Bangalore, Karnataka
Job Summary
Candidates with minimum 15 years experience is mandatory
Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems.
Establish, standardize, and continuously improve engineering methodologies, automation scripts, and best practices across the organization.
Experience in Full chip RTL integration
Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc.
Experience in RTL Synthesis
Scripting experience
Experience integrating IP's like PCIe, DDR, Ethernet etc.
Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there.
Expected to handle minimum 3 projects simultaneously
Experience in handling and interacting with clients across different Geos.
Excellent communication skills are mandatory.
Should be able to interact with leads of different disciplines and able to work in a collabarative manner with different SPOCs
Key Responsibilities
1. Guide and implement memory layout design solutions using industry-standard EDA tools and scripting languages, ensuring optimal performance and adherence to technical standards.
2. Provide technical direction and support to team members in memory layout design, utilizing tools such as Cadence Virtuoso or Synopsys Custom Compiler for effective layout creation and validation.
3. Ensure process compliance in layout design activities by applying DRC/LVS checks and following established design flows in the assigned module.
4. Participate in technical discussions and feasibility studies, leveraging expertise in memory layout design to evaluate technical alternatives, assess tool compatibility, and identify design risks.
5. Prepare and submit project status reports focused on memory layout deliverables, proactively addressing potential risks and supporting escalation resolution within the design domain.
Skill Requirements
1. Solid proficiency in memory layout design methodologies and flows.
2. In-depth knowledge of EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, or Mentor Graphics for layout creation, verification, and optimization.
3. Strong understanding of DRC/LVS checks, parasitic extraction, and design-rule compliance.
4. Ability to script using SKILL, Python, or TCL for automation in layout design tasks.
5. Experience advocating and applying best practices and technical standards within memory layout projects.
Other Requirements
1. Optional but valuable: Certification in VLSI Design or Custom Layout Design (e.g., Cadence Certified Layout Designer).
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