Date posted 05/24/2026
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years building verification environments that have to actually catch the bugs that matter, not just hit coverage numbers. The difference between IP that ships and IP that gets pulled back is often a corner case you thought to test in week three, and you are the kind of engineer who builds that test before anyone asks for it.
You are comfortable moving between System Verilog testbenches, UVM architecture decisions, and protocol-level debugging without losing sight of what you are actually proving. PCIe is not just a spec to you, it is a set of real-world failure modes you have seen, debugged, and prevented from happening again. You do not wait for a complete test plan to start building, you work with what the RTL team has today, ask the right questions about what is coming next week, and structure your environment so it does not break when requirements shift.
At Synopsys, you will work on DesignWare IP that powers connectivity in everything from data centers to automotive systems. The team is global, the protocols are real, and what you verify will ship.
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Design and implement System Verilog verification environments for DesignWare IP cores, including testbench architecture, stimulus generation, checkers, and coverage models
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Develop and execute test plans for PCIe and other high-speed connectivity protocols, covering unit-level and full system integration scenarios
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Build and debug complex test cases using UVM, ensuring functional correctness and protocol compliance
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Drive functional coverage closure and manage regression suites using VCS, NC, or MTI
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Collaborate with RTL designers to reproduce, root-cause, and resolve design issues with clear verification metrics
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Automate verification flows using Python, Perl, or TCL to improve efficiency and turnaround time
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Deliver verified, production-quality IP cores that enable connectivity in commercial, enterprise, and automotive systems worldwide
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Catch critical design issues early, reducing respins, customer escalations, and time to market
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Set the standard for verification quality and coverage rigor across the DesignWare IP portfolio
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Mentor junior verification engineers and
