About the Role
The candidate would own and drive the design, implementation, and verify FPGA prototypes of next-generation SOCs. The responsibilities mainly cover the following:
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FPGA integration and implementation of All interfaces (PCIe, DDR, etc)
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FPGA implementation and timing closure
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Provide emulation Platform solution for FW development
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Provide emulation Platform for Pre silicon Validation
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FPGA Validation and debug
Key Requirements
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Hands on design experience using Verilog, System Verilog and porting large designs to FPGA including combination of custom RTL as well as proven IP cores.
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FPGA experience includes implementation, synthesis (Synplify/Vivado), timing closure using Vivado.
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Ability to partition a big AISC design into multiple FPGA sub-systems and implement modules for interconnection between these sub-systems.
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Proficiency in Perl, Tcl language.
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Good hardware debug skills using FPGA debug tools like Chipscope and lab debug equipment like Oscilloscopes and Logic Analyzers to root cause issues at silicon or board level.
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Hands on experience using PCIe controller, DMA and working knowledge of AXI protocols and ARM is required
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Ability to work closely with software team and get involved in hardware-software co-debug.
