Candidate should have worked on Finfet technology layouts. Exposure to technology nodes like 3nm/5nm and 7nm is required.
Candidate should have 6+ years of experience in custom layout. Experience on high-speed analog mixed-signal layout is desirable.
Role:
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Candidate will own and Lead Major blocks of Memory PHY Layout design.
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Candidate would perform hand-on design of critical analog and high-speed layout blocks.
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Candidate would co-ordinate design work with Circuit leads, layout contractors and layout team members.
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Candidate would participate in layout reviews by presenting and reviewing custom layout designs.
