About Edgecortix
EdgeCortix is driving innovation in semiconductor solutions for the connected intelligent edge. Established in 2019 and headquartered in Tokyo, Japan, with additional offices in the United States and India, the company develops silicon-based, energy-efficient AI processors purpose-built for Generative AI workloads at the edge. The company’s patented hardware-software co-design methodology enables highly efficient runtime-reconfigurable AI accelerators, delivering industry-leading performance-per-watt for edge inference across defense, aerospace, smart cities, Industry 4.0, robotics and telecommunications applications.
The Team
As an engineering driven company we are working to define and solve the hardest problems at the intersection of AI, semiconductors and scalable systems across the edge computing landscape. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency and cost-efficiency for AI inference infrastructure across markets like robotic, industrial automation, aerospace & defense and telecommunications.
The Role
As the Physical Design Lead, you will own the physical implementation strategy for AI SoCs, chiplets, and IP blocks while providing technical leadership to the Physical Design team and external implementation partners. You will drive Power, Performance, and Area (PPA) optimization, implementation methodology, and design closure from RTL to GDSII, ensuring high-quality silicon delivery.
Key Responsibilities
The responsibilities of this role include, but are not limited to:
- Lead the end-to-end physical implementation (RTL-to-GDSII) of AI SoCs, chiplets, and hardened IP blocks, ensuring successful tape-out with optimal Power, Performance, and Area (PPA).
- Provide technical leadership to the Physical Design team and guide external implementation partners to ensure high-quality and timely project execution.
- Drive synthesis, floor planning, placement, CTS, routing, STA, timing closure, and sign-off across multiple PVT corners using industry-standard Synopsys and Cadence tools.
- Develop, maintain, and continuously improve physical design methodologies, implementation flows, automation, and best practices.
- Evaluate standard cell libraries, implementation methodologies, and technology options to maximize PPA and implementation efficiency.
- Continuously optimize PPA through improvements in architecture, logic implementation, synthesis, floor planning, routing, libraries, and technology selection.
- Own power planning and analysis, including UPF implementation, power grid generation, IR-drop, EM analysis, power budgeting, and power integrity.
- Develop and optimize implementation constraints (SDC, TCL), perform timing analysis, resolve timing bottlenecks, and drive ECO implementation.
- Define floor planning strategies and hierarchical partitioning for complex SoCs and chiplet-based designs.
- Collaborate closely with Architecture, RTL, Verification, DFT, and Product Engineering teams, providing continuous implementation feedback to improve system-level PPA.
- Participate in early architecture studies, implementation feasibility analysis, PPA estimation, and power/area budgeting for future products.
- Drive sign-off quality by reviewing implementation reports, timing, power, congestion, DRC/LVS readiness, and physical verification metrics.
- Coordinate with external backend implementation partners, review deliverables, and ensure execution aligns with project milestones and quality standards.
- Stay current with emerging semiconductor technologies, EDA tools, and implementation methodologies, driving innovation and continuous improvement across the Physical Design flow.
- Mentor and support junior engineers while fostering technical excellence within the Physical Design team.
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 8+ years of experience in physical design of complex SoCs with strong expertise in synthesis, timing closure, and physical implementation.
- Proven experience in RTL-to-GDSII implementation using Synopsys and/or Cadence EDA tools.
- Strong expertise in STA, synthesis, floorplanning, CTS, P&R, MMMC, DVFS, and low-power implementation (UPF).
- Experience with advanced technology nodes (12nm and below).
- Strong scripting skills using TCL, Python, and Shell.
- Experience working with external implementation teams or design service partners.
Preferred Qualifications
- Master's degree in Electrical Engineering or a related discipline.
- 10–15+ years of experience in Physical Design or SoC implementation.
- Experience leading physical implementation for multiple tape-outs.
- Experience with AI accelerators, chiplet architectures, or hierarchical SoC designs.
- Strong understanding of DRC/LVS, IR-drop, EM, crosstalk, and physical sign-off.
- Excellent technical leadership, communication, mentoring, and cross-functional collaboration skills.
What’s in it for you?
Make a difference: you will have the opportunity to join a well-funded and rapidly growing fabless AI semiconductor company that is disrupting the AI software and hardware across the edge AI landscape. Be an integral part of its growth and momentum.
Location - Hyderabad
Benefits and Perks
- Highly competitive salary and stock options (as applicable)
- Flex work time
- Top-tier employee benefits
