Description of the Role:
In this role as a Lead Engineer (FPGA Verification Engineer, Actuation Systems) actively contribute towards requirement-based testing (RBT) in FPGA verification using System Verilog and UVM methodology, in accordance to DO-254 process.
FPGA JD:
Primary Responsibilities:
1.Develop an effective suite of tests and test environments using System Verilog UVM, based tests to achieve predefined requirement verification goals.
2.Develop test-plan, self-checking test-benches to meet the verification criteria and code coverage.
3.Participate in requirement validation and requirement review.
4.Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing.
5.Actively participate in a team environment, working with verification, architecture, applications, and design teams to develop comprehensive verification plans and address issues.
6.Verification environment development/update for block level and system level.
7.Work closely with design team on design de-bugging, coverage gap analysis etc.
8.Verify structural and functional coverage of module and system level test suite.
9.Advanced skills in various programming languages such as System Verilog/UVM, PERL or any scripting language.
10. techniques and skills required to identify a root cause of a given issue and very good debugging skills.
11.Technical guidance to the junior engineers on verification tasks.
