Job Requirements
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Key Responsibilities
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Perform floorplanning, placement, clock tree synthesis (CTS), and routing
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Handle timing closure (STA) including setup and hold fixes
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Work on power optimization and IR drop analysis
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Perform physical verification (DRC, LVS, ERC)
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Execute ECO implementation and convergence
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Collaborate with RTL, DFT, and STA teams for design closure
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Analyze and fix congestion, signal integrity, and noise issues
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Ensure design meets foundry and sign-off requirements
Required Skills
Technical Skills
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Strong understanding of ASIC/SoC design flow
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Hands-on experience in:
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Floorplanning & Placement
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CTS & Routing
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Static Timing Analysis (STA)
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Power analysis (IR/EM)
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Good knowledge of:
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Process technologies (7nm / 14nm / 28nm etc.)
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Signal integrity & crosstalk
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Scripting skills:
Tools Experience
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Synopsys (ICC2, PrimeTime, Fusion Compiler)
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Cadence (Innovus, Tempus, Voltus)
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Mentor Graphics tools (Calibre DRC/LVS)
Qualifications
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Bachelor’s or Master’s degree in Electronics / VLSI / Electrical Engineering
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2–10 years of experience in physical design (based on seniority)
Preferred Skills
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Experience in advanced nodes ( 16nm)
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Knowledge of low-power design techniques (UPF/CPF)
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Exposure to DFT and chip-level integration
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Experience in multiple tape-outs
Key Performance Indicators (KPIs)
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Timing closure (setup/hold violations)
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Power and area optimization
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Design rule clean (DRC/LVS clean)
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On-time project delivery
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Quality of tape-out
