We are seeking an experienced STA Engineer to join our ASIC design team and drive timing signoff and closure activities for high-performance SoC and subsystem designs. The ideal candidate will possess deep expertise in Static Timing Analysis, timing closure methodologies, signoff flows, and ECO implementation across complex semiconductor designs. This role offers an opportunity to work on cutting-edge ASIC programs in a collaborative and technically challenging environment.
Key Responsibilities
· Perform block-level and full-chip Static Timing Analysis (STA) and timing signoff.
· Drive timing closure for high-frequency blocks and subsystems operating in the GHz range.
· Define and validate timing modes, corners, and constraints required for signoff closure.
· Analyze timing violations and develop effective closure strategies across setup, hold, signal integrity, and variation-related issues.
· Collaborate closely with Physical Design, DFT, Design, and Signoff teams to achieve timing convergence.
· Support ECO implementation and timing validation throughout the design cycle.
· Develop and maintain TCL-based automation scripts to improve timing analysis efficiency and productivity.
· Ensure timing signoff compliance across multiple process, voltage, and temperature (PVT) corners.
· Participate in design reviews and provide technical guidance on timing-related challenges.
Required Skills
· 6+ years of experience in ASIC STA and timing signoff.
· Strong hands-on expertise with:
o Cadence Tempus
o Synopsys PrimeTime
o Tweaker
o DMSA / PTECO environments
· Deep understanding of:
o Timing corners and operating modes
o Process variations
o Signal Integrity (SI) analysis
o Timing signoff methodologies
· Strong knowledge of:
o SDC constraint development and validation
o OCV, AOCV, and POCV methodologies
o Setup and hold timing closure
· Experience with full-chip timing closure and signoff flows.
· Good understanding of DFT timing requirements and timing signoff for test modes.
· Familiarity with Physical Design flows and ECO implementation processes.
· Strong TCL scripting and automation skills.
· Excellent debugging, analytical, and problem-solving abilities.
Preferred Qualifications
· Experience with advanced-node ASIC designs.
· Exposure to large-scale SoC timing closure and signoff environments.
· Understanding of low-power and multi-voltage timing methodologies.
· Experience working in cross-functional design closure teams.
Educational Qualifications
· B.E./B.Tech./M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related field.
Notes
· This requirement is for the AECG ASIC SSD Bangalore team.
· Candidates must have strong hands-on experience in STA signoff and timing closure.
· Expertise in Tempus and/or PrimeTime is mandatory.
· Strong TCL scripting skills are required.
· Please prioritize candidate with full-chip timing closure experience on complex ASIC/SoC designs.
Pay: ₹1,800,000.00 - ₹2,500,000.00 per year
Work Location: In person
