Lead Physical Verification Engineer
Location: Bengaluru
Experience: 6+ Years
Employment Type: Full-Time
Pay: Open for Negotiate for any Digit
Job Summary
We are looking for a Lead Physical Verification Engineer with 6+ years of experience in physical verification and semiconductor design sign-off. The role involves leading DRC/LVS verification activities for complex SoC designs, driving closure of physical verification issues, managing tapeout risks, and working closely with design, methodology, foundry, and technology teams.
Key Responsibilities
- Lead physical verification activities for complex SoC/block-level designs from implementation through tapeout.
- Drive DRC, LVS, ERC, antenna, and related physical verification sign-off activities.
- Develop and execute effective strategies for DRC/LVS debugging, root-cause analysis, and closure.
- Review and resolve complex physical verification violations in collaboration with Physical Design, Layout, and Custom Design teams.
- Own PV sign-off schedules, milestones, risk tracking, and tapeout readiness.
- Collaborate with foundries and technology teams on PDK, rule decks, and novel/advanced technology-node verification requirements.
- Support development, validation, and deployment of physical verification methodologies and flows.
- Analyze verification results and drive automation/improvements to enhance PV efficiency, quality, and turnaround time.
- Mentor junior and mid-level engineers and provide technical guidance on physical verification issues.
- Participate in design reviews, sign-off reviews, and cross-functional tapeout activities.
Required Skills
- 6+ years of experience in Physical Verification / ASIC/SoC Design Verification.
- Strong hands-on experience with DRC, LVS, ERC, antenna, and physical sign-off.
- Experience with industry-standard PV tools such as Calibre, Pegasus, PVS, or equivalent.
- Strong understanding of IC layout, CMOS design, physical design, and semiconductor manufacturing processes.
- Experience debugging complex DRC/LVS violations and driving them to closure.
- Good understanding of foundry rule decks, PDKs, design rules, and sign-off requirements.
- Experience working with advanced technology nodes and complex SoC designs is preferred.
- Strong scripting/automation skills using TCL, Python, Perl, or Shell.
- Excellent problem-solving, communication, and cross-functional collaboration skills.
Preferred Qualifications
- Experience with novel/advanced physical verification methodologies.
- Exposure to full-chip sign-off and tapeout execution.
- Experience interacting directly with foundry/technology teams on rule-deck issues and verification requirements.
- Prior experience leading PV teams or mentoring engineers.
- Knowledge of hierarchical LVS, metal fill, density, ESD, latch-up, and reliability-related checks is an advantage.
Key Competencies
Physical Verification | DRC | LVS | ERC | Antenna | PV Sign-off | Calibre/PVS/Pegasus | PDK | Rule Decks | Tapeout | SoC | ASIC | Physical Design | Python/TCL/Perl/Shell | Foundry Collaboration
Pay: ₹4,000,000.00 - ₹6,000,000.00 per year
Work Location: In person
