Job Requirements
Hardware Physical Design Engineer
Google G Chips is seeking experienced Physical Design Engineers to drive the implementation and optimization of next-generation SoC designs. The role involves owning key aspects of the physical design flow and delivering high-quality silicon that meets aggressive Power, Performance, and Area (PPA) targets.
Key Responsibilities:
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Drive physical design activities including floorplanning, Place & Route (PnR), Clock Tree Synthesis (CTS), and timing closure.
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Perform PPA optimization and resolve timing, congestion, and power-related challenges.
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Develop and validate timing constraints and perform Static Timing Analysis (STA).
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Execute and debug LEC, VCLP, and EMIR signoff checks.
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Collaborate with cross-functional teams to achieve design and tapeout milestones.
Required Skills:
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Strong experience in ASIC/SoC Physical Design and implementation.
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Expertise in PnR, CTS, STA, timing convergence, timing constraints, and PPA optimization.
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Hands-on experience with LEC, VCLP, and EMIR analysis.
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Cadence Innovus experience is mandatory.
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Experience with Synopsys Fusion Compiler is also acceptable.
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Strong debugging, problem-solving, and communication skills.
Preferred:
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Experience with advanced technology nodes (7nm and below).
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Scripting knowledge in Tcl, Perl, or Python.
Location: Taiwan
Experience: 5+ Years
Keywords: Physical Design, PnR, CTS, Timing Closure, STA, PPA, Floorplanning, Innovus, Fusion Compiler, LEC, VCLP, EMIR, ASIC, SoC.
