Software Architect – Virtual & Hybrid Platform Integration and Software Bring-up
Role Overview
We are looking for a seasoned Software Architect to join the team, responsible for Virtual and Hybrid platform integration and pre‑silicon software bring-up. The candidate will work on complex emulator- and FPGA-based platforms to enable early software development and validation for mobile, hyperscale, and automotive SoCs.
This is a hands-on individual contributor role requiring deep technical expertise, strong cross‑functional collaboration, and the ability to independently drive complex technical deliverables from architecture to execution.
Key Responsibilities
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Architect, integrate, and debug Virtual and Hybrid platforms combining RTL, transactors, and virtual models for pre‑silicon enablement.
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Develop systemC and Multithreaded C++ models and Transactors necessary for bringup of software on a Hybrid platform.
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Lead software bring-up on pre‑silicon platforms (emulators / FPGA prototypes), including:
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Bare‑metal environments
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Linux OS
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Android
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Windows (where applicable)
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Drive end‑to‑end platform readiness from early boot (ROM, bootloaders) to OS stability.
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Work closely with RTL, IP, firmware, validation, and customer teams to define requirements, align interfaces, and plan deliverables.
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Debug complex software and platform issues using:
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Waveform analysis
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Software debuggers (GDB, JTAG-based, emulator debuggers, etc.)
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Logs and traces
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Identify root causes across HW/SW boundaries and propose robust architectural fixes.
Technical Expertise & Qualifications
Required Skills
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Strong background in software architecture with proven experience building and debugging complex pre‑silicon platforms.
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Hands‑on experience integrating RTL with virtual and hybrid environments.
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Deep understanding of SoC architecture and system-level behavior across:
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Mobile
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Hyperscaler / Datacenter
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Automotive platforms
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Expert knowledge of AMBA protocols and interconnects.
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Proven experience working with and integrating key SoC IPs such as:
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Strong proficiency in software debugging methodologies, including waveform-based debug and HW/SW co-debug.
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Solid programming and scripting skills (C/C++, Python, shell scripting preferred).
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Hands on experience on Multi-Threaded aspects, its challenges and tools to manage deadlocks
Preferred / Value-Add Skills
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Experience with SystemC modeling and transaction-level modeling; ability to modify or develop models is a strong plus.
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Prior experience working with emulators and FPGA-based platforms (Palladium, Protium, or similar).
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Familiarity with GenAI / LLM-based workflows applied to EDA, debugging, automation, or productivity acceleration.
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Knowledge of platform performance analysis and optimization.
Collaboration & Leadership Expectations
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Strong ability to work across cross‑functional teams and with external customers to:
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Understand complex, multi-team requirements
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Translate them into executable technical plans
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Ability to independently lead and execute projects, owning outcomes end to end.
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While this is an individual contributor role, prior experience in:
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Mentoring junior engineers
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Technical leadership
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Team or project ownership
is highly valued.
Candidate Profile
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A senior, hands-on technologist with strong problem-solving skills and a system-level mindset.
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Comfortable operating in ambiguous, fast‑moving environments.
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Motivated to align with long‑term technical growth and strategic platform evolution within Cadence.
