Noida, Uttar Pradesh
Job Summary
Define ASIC/SoC verification strategy
Full chip testplan development
Full chip TB Architecture definition
UVM based testbench development
SV functional coverage, Assertions coding
C based TB development
Test case development, coding, execution, bug analysis
Gate Level Simulation
Regressions, coverage analysis
Own and execute verification closure
EducationDegree:
Core Technical Skills
Define ASIC/SoC verification strategy
Full chip testplan development
Full chip TB Architecture definition
UVM based testbench development
SV functional coverage, Assertions coding
C based TB development
Test case development, coding, execution, bug analysis
Gate Level Simulation
Regressions, coverage analysis
Own and execute verification closure
Key Responsibilities
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