Bangalore, Karnataka
Job Summary
The Silicon Design Verification Manager is responsible for leading pre‑silicon verification of complex IP, subsystem, and SoC designs , ensuring functional correctness, coverage closure, schedule adherence, and strong customer alignment. The role combines technical depth, customer engagement, team leadership, and delivery governance across large‑scale SoC programs.
Key Responsibilities
Program & Delivery Ownership
Own end‑to‑end DV delivery for IP / Subsystem / SoC‑level verification programs
Drive verification planning, execution, coverage closure, and sign‑off aligned to customer milestones
Ensure monthly and sprint‑wise planning , risk identification, dependency tracking, and mitigation
Accountable for schedule, quality, and billing health , preventing leakage and delivery surprises
Technical Leadership
Demonstrate strong understanding of SoC architecture , block boundaries, and ownership split (HCL vs customer)
Review and guide DV architectures , testbench strategies, reuse, regressions, and coverage metrics
Provide technical oversight for SV/UVM, assertions, formal verification, emulation , and regression flows
Lead debug discussions with RTL, architecture, and post‑silicon teams
Customer Engagement
Act as primary technical interface for DV topics with customer architects and verification leads
Drive clear alignment on scope, estimates, deliverables, and milestones
Proactively handle customer escalations , communication, and expectation management
Lead MBRs / QBRs , ensuring no surprises through strong internal preparedness
Team & Capability Management
Assess and maintain clear visibility into engineer skill levels, expertise, and readiness
Define effective team structures aligned to program complexity and timelines
Mentor DV leads and engineers; drive skill development and succession planning
Partner with CUH / staffing teams for fulfillment, backfills, and risk mitigation
Governance & Reporting
Own MBR metrics , status reports, risk registers, and action tracking
Enforce review cadence on deliverables, regressions, and quality metrics
Ensure compliance to customer and organizational DV processes
Value Creation & Future Readiness
Drive value‑add initiatives : productivity improvements, automation, and quality acceleration
Champion GenAI and tool adoption where applicable in verification flows
Plan buffers and capability ramp‑ups for future SoC programs and technology nodes
Skill Requirements
15+ years in Silicon Design Verification , with experience leading large SoC programs
Strong hands‑on or review‑level expertise in SystemVerilog, UVM, assertions, coverage, and debug
Solid understanding of CPU/GPU, interconnects, memory subsystems, high‑speed interfaces
Proven experience in customer‑facing roles , escalations, and program leadership
Strong people leadership, planning, and cross‑functional collaboration skills
Other Requirements
Predictable delivery with zero billing leakage
Strong customer confidence and fewer escalations
High team utilization, skill maturity, and retention
Tangible value creation beyond baseline delivery
Bachelor’s/Master’s in Electrical/Electronics/Computer Engineering or related field.
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