Role description
Must have a solid understanding of SoC verification flows and experience with SoC verification in multiple clients.
- Should be an independent learner with experience in developing C-based tests for ARC/ARM/RISC-based SoCs.
- Must be an individual contributor capable of managing other CWs.
- Requires a good understanding of SV, UVM test benches, and experience with protocols such as APB, AXI, I2C, UART, PCIe, or DDR.
- Should be able to take the SoC verification test bench and port it for FPGA RTL verification and maintain the test bench for FPGA-RTL.
- Must possess strong debugging skills in SoC Verification.
- Candidates should have 8+ years of relevant experience.
- Candidates should have 5-8 years of relevant experience.
Skills
vlsi design,soc design,systemverilog,asic design,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
