We are seeking a Senior Physical Design Engineer with 6 years of experience to lead the physical implementation of our advanced semiconductor projects. You will play a crucial role in shaping the silicon realization of our cutting-edge designs, ensuring their successful integration from RTL to tape- out.
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Provide technical guidance, mentoring to physical design engrs.
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Interface with front-end ASIC teams to resolve issues.
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Low Power Design – Voltage Islands, Power Gating, Substrate-bias techniques.
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Timing closure on DDR2/DDR3/PCIE interfaces.
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Excellent communication skills.
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Strong Background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
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Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
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Expertise in scripting languages such as PERL, TCL.
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Strong Physical Verification skill set.
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Static Timing Analysis in Primetime or Primetime-SI.
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Good written and oral communication skills. Ability to clearly document plans.
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Ability to interface with different teams and prioritize work based on project needs.
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He/she should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
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He/she should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
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Proficiency in EDA tools for floor planning, place and route, clock tree synthesis, and physical verification.
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Bachelor’s or Master’s degree in electronics engineering or related field
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Familiarity with EDA tools such as Cadence Innovus, Synopsys ICC, Mentor Calibre
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Knowledge of low power design techniques and implementation
