About the job
Job: Analog Layout / Custom IC Layout Engineer
Location: Bengaluru | Noida
Employment Type: Full-time
Experience: Senior-level
Function: Semiconductor Engineering — Analog Layout / Custom IC Layout
About SiliconBoard
SiliconBoard connects semiconductor engineering talent with companies across the semiconductor ecosystem. This opportunity is offered through the SiliconBoard Talent Network. Shortlisted profiles are evaluated and shared with hiring companies within our partner network for relevant open positions.
About the Role
We are looking for experienced Analog Layout / Custom IC Layout Engineers with strong hands-on experience in full-custom layout of analog and mixed-signal circuits.
You will work closely with analog designers to convert schematics into high-quality physical layouts that meet electrical, matching, area, reliability, and manufacturability requirements.
The role involves block-level and top-level layout, physical verification, parasitic-aware optimization, and close collaboration with circuit designers throughout the design and sign-off process.
Key Responsibilities
Custom Layout Design
- Develop full-custom layouts for analog and mixed-signal circuits.
- Translate schematics and design intent into robust physical layouts.
- Work on device placement, routing, shielding, symmetry, and matching requirements.
- Optimize layouts for area, performance, reliability, and manufacturability.
- Ensure proper handling of sensitive analog signals, clocks, references, and power supplies.
Device Matching and Layout Techniques
- Apply matching techniques such as common-centroid placement, interdigitation, symmetry, and dummy devices.
- Minimize systematic mismatch and process-gradient effects.
- Understand the impact of parasitics and physical proximity on circuit performance.
- Work closely with analog designers on layout-dependent effects and sensitive device structures.
Block and Top-Level Layout
- Own layout of analog blocks, custom IP, and mixed-signal modules.
- Support integration of multiple analog blocks into larger subsystems or top-level designs.
- Handle floorplanning, block placement, interface routing, and supply planning.
- Coordinate with design and integration teams to resolve physical and electrical constraints.
Physical Verification
- Perform and debug DRC, LVS, ERC, antenna, and density checks.
- Resolve physical verification violations and drive clean sign-off.
- Ensure layout compliance with foundry and process design rules.
- Support reliability checks such as electromigration and current-density analysis where required.
Parasitic Extraction and Post-Layout Support
- Perform parasitic extraction and support post-layout simulation.
- Work with analog designers to analyze layout-induced performance degradation.
- Optimize routing, device placement, and parasitics based on simulation results.
- Support iteration between schematic, layout, and post-layout verification until design closure.
Power, Reliability, and Signal Integrity
- Design robust power and ground routing for analog and mixed-signal circuits.
- Consider IR drop, electromigration, noise coupling, substrate noise, and shielding requirements.
- Implement guard rings, isolation structures, and other noise-control techniques where required.
- Support high-voltage, high-current, or sensitive low-noise layouts depending on the design.
Design Closure and Tapeout
- Support layout reviews and sign-off activities.
- Work with design, verification, and integration teams to resolve last-mile issues.
- Prepare layouts for final tapeout.
- Support engineering changes and layout updates during design closure.
Required Qualifications
- B.E./B.Tech, M.E./M.Tech, Diploma, or equivalent relevant experience in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
- Strong hands-on industry experience in Analog Layout / Custom IC Layout.
- Experience with full-custom layout of analog or mixed-signal circuits.
- Good understanding of device matching, symmetry, routing, and parasitic effects.
- Hands-on experience with DRC and LVS closure.
- Familiarity with parasitic extraction and post-layout simulation flows.
- Understanding of analog circuit behavior and layout-dependent effects.
- Ability to read and understand schematics and work closely with circuit designers.
- Strong debugging skills for physical verification and layout-related issues.
Preferred Qualifications
Relevant experience in one or more of the following areas:
- ADC / DAC layout
- PLL / DLL layout
- LDO and power management layout
- Bandgap reference layout
- Op-amp and comparator layout
- SerDes analog layout
- High-speed I/O layout
- PHY layout
- Analog front-end layout
- Sensor interface layout
- Clocking circuits
- Memory peripheral layout
- Custom digital layout
- RF or high-frequency layout
- Mixed-signal top-level integration
Experience in the following areas is also preferred:
- Common-centroid and interdigitated layouts
- Guard rings and substrate isolation
- Deep N-well structures
- High-voltage device layout
- Low-noise layout techniques
- Parasitic-aware layout optimization
- Electromigration and reliability-aware layout
- Advanced CMOS process nodes
- Multiple power domains
- Hierarchical custom layout
- Top-level analog integration
- Multiple successful tapeouts
Experience working with industry-standard custom layout and physical verification tools such as Cadence Virtuoso, Synopsys Custom Compiler, Siemens Calibre, Cadence Pegasus, or equivalent platforms is preferred.
Hiring Process
- Submit your resume through the application link.
- Profiles are manually reviewed and shortlisted by the SiliconBoard team.
- Shortlisted candidates may receive a technical screening or AI-based technical interview.
- Qualified profiles are shared with the hiring company for the next stage of the process.
Additional Information
This opportunity is with a SiliconBoard client company and not with SiliconBoard directly.
Compensation is determined by the hiring company based on role, experience, technical depth, and interview performance.
Submission of an application does not guarantee an interview, referral, or employment.
Profiles are evaluated based on layout ownership, circuit type, process-node experience, matching techniques, DRC/LVS expertise, parasitic awareness, block complexity, top-level integration, tapeout experience, and the requirements of the hiring company.
Pay: ₹298,748.71 - ₹1,400,060.09 per year
Work Location: In person
