- Perform RTL synthesis using standard EDA tools.
- Run Static Timing Analysis (STA) to check timing performance.
- Identify and fix setup and hold timing violations.
- Work with design and physical design teams to achieve timing closure.
- Optimize design for timing, area, and power.
- Prepare and review timing and synthesis reports.
Pay: ₹200,000.00 - ₹2,000,000.00 per year
Benefits:
- Health insurance
- Paid sick time
Work Location: In person
