DFT Engineers
Location - Bangalore
Experience - 8 to 15yrs
- RTL DFT insertions & verification
- SSN implementation and validation
- IJTAG (IEEE 1687) insertion & verification – Block and SoC level
- MBIST insertion, memory repair configuration & verification – Block and SoC level
- EDT-based scan compression insertion and validation
- Netlist insertions & Pattern verification
- Gate-level scan stitching and DRC checks
- LBIST architecture implementation and validation
- ATPG pattern generation (stuck-at/transition) and GLS simulations
- Coverage analysis, debug, and pattern optimization
Pay: ₹1,000,000.00 - ₹2,500,000.00 per year
Work Location: In person
