Job Requirements
Job Summary:
We are looking for a highly skilled and hands on Lead Engineer to lead and drive Subsystem/SOC Design Verification for an ARM based SoC Design.
Extensive experience in SV/UVM based SOC or IP Verification.
Key Responsibilities:
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Own and delivery IP/Subsystem/SOC Testbench development, define Test plan, Test development & debug.
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Strong knowledge in CPU based SOC architecture.
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Develop and execute System Verilog/UVM Testbenches for SOC/IP Verification
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Develop SV/UVM based SOC/IP Testbench & Implement and run directed, random, and constrained random tests
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Analyze & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution.
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Define Functional/Code/Assertion coverage metrics, sign-off checklist and drive to closure.
Work Experience
Required Skills:
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8+ years of hands-on experience in IP/SOC Verification with Strong SOC Architecture knowledge
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Proficiency in SV/UVM based testbench development and constrain random verification.
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Familiarity with standard verification tools ( VCS, Xcelium) and debug environment
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Scripting skills ( Python/Perl)
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Strong debugging, analytical and problem-solving skills
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Experience in two or more High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)
Optional Preferred Skills
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Exposure to Formal Verification or assertion-based verification.
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Power aware verification ( UPF)
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GLS & Xprop runs
