Design Verification (Cache)
Location: Bangalore
Job Description:
- Strong knowledge of cache architecture & memory hierarchy
- Hands-on experience with SystemVerilog & UVM
- Good understanding of SoC interconnects (AXI / ACE / CHI)
- Experience in protocol verification and debug
- Solid fundamentals in computer architecture
- Familiarity with coverage-driven verification methodologies
Experience (years) : 4+ years
Education Qualification:
BE/ME
