Role description
Experience- 9+yrs
- Xilinx FPGA - Versal and Ultrascale families
- Handling large SOC design and familiarly with VCS, Xcelium tools
- Proficient in Verilog/ System Verilog and Test benches.
- Experience in HAPS emulation - HAPS100 or HAPS200 ,protocompiler flow.
- Hands on experience in bring up of PCIe, SPI, I2C, DDR interfaces and strong experience in debug.
vlsi design,soc design,systemverilog,asic design,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
