Role description
Job Description: Title: STA engineer required Role and Responsibilities: Candidate should be able to run STA tools ( Synopsys tools preferred) independently, understand STA methodology and debug STA issues. Candidate is also expected to generate ECO across MCMM, analyse ECO quality and give feedback to design team during fix . Hands on knowledge on ICC2, FC is desirable. Candidate should also be able to understand different design metrics . Should have adequate knowledge on .lib generation and analysis of different fields inside .lib/.db . He/She should have good scripting knowledge as well (Tcl, perl , python etc ) Skill Requirements: STA Good to have: PD, circuit simulation , scripting knowledge Experience: 2-4 Years Qualifications: B.Tech/B.E/M.Tech/M.E
Skills
Static Timing Analysis, Tcl, Physical Design, Perl
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
