Physical Verification Engineer
Location: India (Hybrid/Onsite)
Job Description:
- Hands on experience in Tessent DFT RTL insertion, DRC checks and debug is a must.
- Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation.
- Working knowledge of timing enabled GLS and related debug.
- A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST controllers, IJTAG, IEEE 1600 standard, and Boundary scan.
- Should be able to handle tasks independently.
- The candidate needs to have good debug skills and should be able to communicate related issues to the larger team.
- Working knowledge of TCL is an add-on.
Skills/Experience:
- Hands on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools
- Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required.
- Working experience in cutting edge technologies such as 3/4/5nm and 7nm process nodes is desired
Experience (years) : 4+ Year
Education Qualification:
B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent
