Expertise in low-level C programming & debugging for embedded systems.
Prior experience and/or exposure to testing platforms (Simulation and/or Emulation)
Familiarity with memory industry standards and technologies such as JEDEC, SPD Data, I2C/I3C, DDR4/5, LPDDR4/4x/5/5x UDIMM, RDIMM, LRDIMM, 3DS, ECC, Mode Registers, Self-Refresh, etc.
Experience with or knowledge of DRAM Initialization/training algorithms, memory timings, addressing, overclocking, etc.
Experience in debugging memory initialization and training issues.
Good understanding of firmware development cycle, integration and verification/validation for pre-si and post-si for SoC designs.
Ability to methodically root-cause complex failure mechanisms at the IP, subsystem and/or system level.
Prior involvement in board, processor, or ASIC bring-up.
Experience in hardware/software interfaces and debugging sophisticated issues in CPU and firmware using JTAG, source code debuggers and other tools.
Experience with source control systems including git/gerrit