Role description
Hands on verification experience with C/C++/SystemVerilog testbench development.Hands on experience with coverage planning, coding and coverage closure.Experience with x86, ARM or any other industry standard microprocessor ISA.Experience with Cache, Coherency and Data-Consistency verification.Experience in clocking, reset, power-up sequences and power management verification.Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.Understanding of low power design verification techniques is a plus.
Skills
vlsi design,microprocessor isa,systemverilog,c,testbench development,coding,x86,coverage planning
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
