Bangalore, Karnataka
Job Summary
Verification engineer for DV SoC - TVP
Key Responsibilities
Development and maintenance of UVM testbenches, including agents, sequences, scoreboards, monitors, and checkers
Skill Requirements
- ASIC IP-level verification using SystemVerilog and UVM testbench
development and maintenance
- Test planning, execution, and closure at IP level
- Writing and debugging constraint-random tests
- Development and analysis of functional coverage and code coverage
- Strong Debugging Skills
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