Job Title: Sr Staff DFT Engineer
Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India office)
Job ID: AI2435
Job Description:
Key Responsibilities:
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Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG
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Develop and execute test insertion flow for scan, MBIST, JTAG
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Estimate and achieve targeted test coverage.
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Run RTL and gate-level simulation for all DFT modes.
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Develop and debug timing constraints for all DFT modes.
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Verify test patterns pre-silicon and post-silicon
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Write scripts in TCL and Perl to achieve productivity enhancements through automation.
Required Background:
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BSEE/MSEE or equivalent degree with 7+ years of experience.
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In-depth knowledge of VLSI design as well as hardware description languages such as Verilog.
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Experience with complex block-level and SOC-level DFT execution in advanced finFET technology.
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Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
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Good problem solving and debug capabilities is a preferred plus.
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Good knowledge of hardware simulation tools like VCS, Verdi, etc.
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Proficient in scripting languages (C/C++/TCL/Perl/Python)
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Should be proficient at working with cross functional and cross site teams.
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Must possess good communication skills, be a self-driven individual and a good team player.
Personal attributes:
Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.
