Job Requirements
Senior Design Verification Engineer | 4 Years Experience
4 years of experience in ASIC/SoC Design VerificationStrong hands-on experience with SystemVerilog and UVMDeveloped and maintained UVM testbenches, sequences, drivers, monitors, and scoreboardsPerformed block-level and subsystem-level verificationExperienced in test plan creation, coverage analysis (functional & code coverage), and closureWorked on debugging RTL and testbench issues using simulators (VCS / Questa / Xcelium)Good understanding of AMBA protocols (AXI / AHB / APB) (if applicable)Experience in regression runs, bug tracking, and verification sign-offCollaborated closely with design, validation, and architecture teamsFamiliar with version control (Git/Perforce) and CI/regression flowsMentored junior engineers and supported reviews
Work Experience
Key Skills
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SystemVerilog, UVM
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Functional Verification
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Coverage-driven Verification
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Debug & Root Cause Analysis
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ASIC / SoC Verification Flo
