Qualification
B.E. in Electronics; M.Tech in VLSI Design
Experience
Experience in CMOS design, low-power optimization, and SPICE simulation using Cadence Virtuoso. Research experience in ML-assisted power and timing optimization.
Knowledge
Strong foundation in Digital IC Design, Low-Power CMOS Circuits, RTL Design, Static Timing Analysis (STA), Machine Learning for Hardware Security, and Cadence-based Layout Design.
Skills
EDA Tools: Cadence Virtuoso, Cadence Genus, Cadence Innovus, Xilinx Vivado. Hardware Description Languages: Verilog (RTL), SystemVerilog. Technical Skills: Digital Logic Design, CMOS Design, SPICE Simulation, Low-Power Optimization, RTL Development, STA.
Pay: From ₹29,000.00 per month
Benefits:
Work Location: Remote
